1. Field
The present application relates to semiconductor dice manufacturing, and more particularly to selecting dice to be test using a yield map.
2. Related Art
Semiconductor devices are typically manufactured by fabricating the devices on a semiconductor wafer. An individual device is formed as a die on the wafer using known semiconductor fabrication processes. Depending on the size of the die, a single wafer can contain hundreds of dice. The dice are generally arranged in a pattern (i.e., a die placement) on the wafer to maximize the number of dice on the wafer.
After the dice are fabricated on the wafer, the dice are electrically tested. Dice that pass the electrical testing are sorted from the dice that fail the electrical testing. The cost of testing can contribute to 30 percent and more of the overall cost of the devices. Semiconductor manufacturers are increasingly performing comprehensive testing of dice, meaning that each die is tested, while the dice are still on the wafer. This process enables the manufacturers to track the locations of the dice that fail or have low yield. However, performing comprehensive testing of dice increases the overall test time and cost.
In one approach to reducing the amount of time needed and cost associated with testing, areas on a wafer that are found to have high yields are no longer tested. For example, after testing dice on a number of wafers, if an area is found to have a high yield, such as greater than 90 percent, dice in that area are no longer tested in subsequent wafers. One shortcoming to this approach, however, is that the fabrication process can drift, which can decrease the yield of the dice in the area not being tested. However, for the very reason that dice in this area are not being tested, the change in the fabrication process and the yield of these dice may go undetected.